Conventionally, semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6 F2 and 8 F2, where F is a minimum feature size. However, DRAM is relatively slow having an access time commonly near 20 nanoseconds (“ns”). SRAM access time is typically an order of magnitude faster than DRAM. Though, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, thus leading to a cell size of approximately 60 F2 to 100 F2.
Others have introduced memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor cell, to minimize the size of a conventional SRAM memory. A thyristor-based random access memory (“RAM”) may be effective in memory applications. Additional details regarding a thyristor-based memory cell are described in U.S. Pat. Nos. 6,767,770 B1 and 6,690,039 B1.
A thyristor-based memory cell may be periodically pulsed to maintain state. Additional details regarding periodically pulsing a thyristor-based memory cell to restore state of such a cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504. Charge leakage out of a thyristor-based memory cell negatively impacts a restore rate of such cell. The more frequent the restore pulsing to maintain state, the more power that is consumed.
Accordingly, it would be desirable and useful to provide means to reduce charge leakage of a thyristor-based memory cell to allow for less frequent restoration pulsing.